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Hewlett-Packard claims that it has achieved a breakthrough in Nano chip technology that will significantly enhance consumer electronics.
The research may result in the creation of chips that are as much as eight times denser than those being produced now, while requiring less energy, using nano technology, the Palo Alto, California-based company said today in a statement.
The cost of making chips is rising because of the expense of increasing production tolerances. Hewlett-Packard said it aims to limit costs by raising the density of field programmable gate arrays, or FPGAs, without the need for higher tolerances.
“The expense of fabricating chips is increasing dramatically with the demands of increasing manufacturing tolerances,” Greg Snider, senior architect at Quantum Science Research, HP Labs, said in the statement. “This approach could increase the usable device density of FPGAs by a factor of eight, using tolerances that are no greater than those required of today’s devices.”
FPGAs are integrated circuits with programmable logic components and interconnects that can be adapted by end-users, Hewlett-Packard said. The chips can be built in current fabrication facilities after “minor” changes because they can be made using the same-sized transistors as those used in current FPGA, design, the company said.
Hewlett-Packard said it expects to have a laboratory prototype of the chip completed “within the year.”
Moore’s Law
Shares of Hewlett-Packard fell 33 cents to $43.20 at 4:02 p.m. in New York Stock Exchange composite trading. They gained 44 percent last year.
The global semiconductor industry, which the Semiconductor Industry Association said had sales of $225.1 billion through the first 11 months of 2006, is approaching the likely limit of Moore’s Law, a theory that has driven engineers to design smaller and faster chips for four decades.
Intel Corp. co-founder Gordon Moore discovered that engineers could double the performance of microprocessors about every two years by shrinking the size of the circuits that carry electrons across silicon wafers, thereby increasing the number of transistors on a single chip.
Intel’s first microprocessor in 1971 contained 2,300 transistors, compared with the recent Montecito chip, which has 1.7 billion transistors on a piece of silicon the size of a postage stamp. Today, most Intel chips have wires 65 nanometers thin. The Santa Clara, California-based company said in June it will move to 45-nanometer wires in most products by the end of 2007.
Nano technology Focus
Manufacturing becomes difficult with anything smaller than about 20 nanometers. Engineers agree Moore’s Law will collide with the physical limitations of materials in the next 10 or 15 years.
A nanometer is a millionth of a millimeter and is used to measure the width of a circuit on a chip. The smaller the distance, the bigger the number of semiconductors that can be cut from one wafer. The smallest mass-produced chips currently available use 65-nanometer technology.
Today’s manufacturing process, known as complementary metal-oxide semiconductor technology, or CMOS, isn’t able to control ever-tinier circuits because the properties of silicon and the circuits change when used in such minuscule amounts.
Given the barrier, chipmakers are studying how to build the basic elements of semiconductors from the atomic level up. They’re using nanotechnology tools such as the scanning tunneling microscope that let engineers study atoms’ behavior and figure out the best ways to manipulate them.
